H7: Universal Gates

Time Estimate1-2 hours   Grade Impact1%   DueSep 14 @ 12pm  

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Notes

Show your work. You must show all steps of your work for full credit. While calculators can perform these calculations, demonstrating your process ensures understanding and mastery of the concepts.

Notation. To encourage flexibility between notations, the problems in this assignment use a variety of notations. We have discussed each style already; review the textbook or your notes if you need help.

Exercises

1. Explain how a NOT gate can be constructed using only NAND gates, and provide the corresponding Boolean expression for this construction.

2. Construct an OR gate using only NAND gates. Draw the gate-level schematic and give the Boolean expression showing how the NAND arrangement implements OR.

3. Construct an AND gate using only NOR gates. Provide the Boolean expression and a brief explanation of why the NOR-only network implements AND.

4. Given the Boolean function $F(A,B,C) = (A \land B) \lor (\lnot A \land C)$, implement $F$ using only NAND gates. Show the transformed NAND-only expression and a simple schematic.

5. Given the Boolean function $G(A,B,C) = (A \lor B) \land \lnot C$, implement $G$ using only NOR gates. Provide the NOR-only expression and truth table for $G$.

6. Use De Morgan’s laws to show how a 2-input XOR gate can be implemented using only NAND gates. Provide the Boolean expression for XOR in terms of NAND operations and a short explanation.

7. For the function $H(A,B,C,D) = (A \lor B) \land (C \lor D)$, design a minimal NAND-only implementation. Show intermediate steps of algebraic manipulation and the final NAND network.

8. Compare the number of gates required to implement a 3-input majority function $M(A,B,C)$ (output 1 if two or more inputs are 1) using (a) only NAND gates and (b) only NOR gates. Provide both implementations and count gates of each type.

9. A student claims any combinational logic can be implemented using only NAND gates but wants to minimize propagation delay. Explain the trade-offs involved when using only NAND gates versus mixed gates, and describe one strategy to reduce delay in a NAND-only design.

10. Find the minimum-cost circuit consisting of only two-input NOR gates that implements the function $F(x_1, \ldots , x_4) = \sum m(6,7,8,10,12,14,15)$. Assume that the input variables are available in both uncomplemented and complemented forms. Show the Karnaugh map, the simplified expression, and the final NOR-only circuit diagram. (Hint: consider the complement of the function).